An improved model is proposed based on the transient power law model under Human Body Model (HBM) stress. This model can predict the gate oxide breakdown statistically under HBM stress. Through HSPICE simulation tool, the corresponding DC effective voltage on the MOS can be calculated. The scatter chart of the precharge voltage of the HBM circuit with the effective DC voltages of the MOS shows a linear relationship. Using the Laplace transform, the linear relationship is proved. Compared with the existing transient power law model, the improved model reduces the computational complexity under the HBM stress and is easier to predict the MOS gate oxide breakdown statistically. The proposed model provides an important reference for the evaluation of the reliability of the MOS gate oxide under the impact of HBM.

The stomatal traits of eighteen dominant woody plants in the Nutrient Enrichment Experiments in Chinese Forests (NEECF) were compared. The results showed that the lifeform affects stomatal features of the woody plants significantly (P<0.05). There is a visible latitudinal pattern of stomatal traits of dominant woody plants in eastern China and MAT, MAP, PET are important influent factors. All woody plants’ stomatal traits have significant correlation. The stomatal length and density showed negative correlation, and the stomatal conductance increased with increasing stomatal length and decreased with increasing stomatal density. Woody plants of different climate zones and lifeform showed diverse response with nitrogen addition.

Based on comprehensive analysis of field work, petrological and geochemical characteristics, the authors study the sources of dolomitizing fluids and the models of dolomitization of the Lower Ordovician Penglaiba Formation in Tongguzibulong Outcrop, the northwestern margin of Tarim Basin, China. Four types of
dolomite are recognized: euhedral-subhedral powder crystallized dolomite, euhedral-subhedral fine crystallized dolomite, subhedral-xenotopic medium crystallized dolomite and subhedral-xenotopic coarse crystallized dolomite. Powder-fine crystallized dolomite is distributed in the lower part of Penglaiba Formation, and has cloudy center surrounded by clear rim. With residual sand texture, inter-crystal pores and inter-partical pores, medium-coarse crystallized dolomite is distributed in the upper part of Penglaiba Formation. The REE patterns of dolomite and contemporaneous limestone rich in LREE and deplete in HREE, present a trait of unobvious Ce anomaly and Eu negative anomaly, the values of C-O isotope locate in the scope of contemporaneous marine dolomite, and Eu negative anomaly. All these denote that the dolomitizing fluid is normal or slightly concentrated seawater. Besides, Powder-fine crystallized dolomite present a low value of Fe, Mn and a high value of Sr, Ba, formed by reflux seepage dolomitization in penesaline seawater. Cloudy center surrounded by clear rim texture and multi-rimmed texture are the results of over-dolomitization. Medium-coarse crystallized dolomite with residual grain texture, interbedded with sand limestone, are controlled by high frequency sea level change. With a higher value of Fe, Mn and a lower value of Sr, Ba when compared with powder-fine crystallized dolomite, medium-coarse dolomite formed by the early reflux seepage dolomitization and intensified by the subsequent burial recrystallization.

Based on the existing equivalent formula of the transmission line pulse (TLP) and IEC 61000-4-2 stresses, the authors propose an analysis method of the system-level model with TLP stress as an input. Compared with the traditional analysis method under system-level IEC stress, the proposed method solves the issue that the calculation of the residual energy flowing into the device under test (DUT) is not accurate enough. Meanwhile, the prediction ability for the failure of the DUT is promoted. This work predicts the failure of the DUT under the mentioned two stresses through SPICE simulation. Furthermore, this work shows the validation through the measured results of the relevant printed circuit boards (PCBs), which confirms the promotion of the aforesaid prediction ability.

Three methods, which are approximate Lie symmetry method, approximate Noether symmetry method and approximate Mei symmetry method, are adopted to study the first order approximate symmetries and approximate conserved quantities of a typical perturbed mechanical system. Six identical first order approximate symmetries and approximate conserved quantities of the typical perturbed mechanical system are obtained by approximate Lie symmetry method and approximate Noether symmetry method, but only five of them can be obtained by approximate Mei symmetry method.

A new structure of RAM type latch is proposed in which parallel charging branches are used to solve the contradiction of the switching current and the charging speed. Compared with the conventional structure, new latch can maintain a relatively high rate of charging and reduce the short-circuit power. Furthermore only one MOS transistor is needed as clock load, saving the power consumption of clocking. HSPICE simulation results show that the proposed RAM n-Latch and p-Latch exhibits 12.8% and 25.5% speed improvement, 19.8% and 26.9% PDP (power-delay product) reduction compared to reported structure.

A new fast and low power current mode SRAM (static random access memory) sense amplifier is proposed. The proposed SA (sense amplifier) is composed of two stages. It can amplify the signal to full swing fast by using a latch based high speed amplification stage. With the current conveyor, the novel SA cuts off the DC path, and therefore it reduces the DC power consumption. The simulation results show that the new SA can provide 17% improvement in the speed and consume 86% less energy than WTA sense amplifier, based on an industry standard 1.0 V/65 nm CMOS technology.

A volumetric display system based on FPGA and DLP technologies is raised. FPGA is used to construct the graphical processing unit, controlling and propagating video streams synthesized after image dithering and layer combined algorithms. This video stream is passed down inside the FPGA through SD card controlling unit, DDR2 high speed memory control, pixel frame converter and HDMI high resolution signal transmitting modules. Afterwards, the video stream is captured by the receiving end of the DLP projector, inside the projector’s video decoding module, the digital electrical signal is converted to light signal and projected to a spinning display underneath. This method allows the viewer perceiving a multi-angled 3D image hovering in air without the wearing of special glasses.

A new flash sense amplifier (SA) is presented, which has a fast pre-charge speed, low power and low supply voltage. Compared to the conventional low-voltage SA, the novel amplifier uses two inverters to improve pre-charge speed by feedback-control pre-charge circuit and to reduce power consumption by taking place of the current source module in reference voltage generation circuit, respectively. In 65 nm CMOS process, the pre-charge time of novel circuit is improved above 15%, and the power dissipation is lowered about 14%.

A novel electrostatic discharge (ESD) power clamp circuit with ultra-low leakage current is proposed. An ESD transient detective circuit with feedback loop is used to reduce the voltage between the bulk and gate of MOS capacitor, which results in a ultra-low leakage current performance of novel circuit. Verified by HSPICE simulation in 65 nm CMOS process, the standby leakage current of novel circuit is 24.13 nA, which is more than two-orders lower than that of the traditional design about 5.42 μA.

A single-ended nine-transistor (9T) SRAM scheme is proposed for sub-threshold operation. The new SRAM cell provides high stability using disturb-free read operation. With a new write mechanism, the cell can solve the pseudo-read problem. Thus, the bit-interleaved structure can be used to address the multiple bit soft-errors problem. Simulation result shows that the SRAM cell can provide 100 mV read static-noise-margin (SNM) and 70 mV worst half-select SNM, when the supply voltage is 300 mV.

A low latency endpoint implementation scheme compliant with specification V1.3 is described. A novel architecture is proposed where most modules in transmitting and receiving paths are designed to work in cut-through modes with the purpose of generating short and fixed latencies. To the transaction interface, requests and responses can be issued from different user-defined ports and sent through the proposed sharable transfer paths. Concurrent transactions can be kept in order by safety arbitration mechanisms. Furthermore, abandoned packets can be cancelled by the enhanced four-queue buffers to prevent invalid transmissions. To the 1x/4x serial physical interfaces, reliable transmissions of packets and control symbols are achieved. Crucial link managements including flow control, error detection and recovery are also supported. Compared with the reference designs, the proposed scheme can achieve lower latency and higher throughput performances. Furthermore, the feasibility and effectiveness have been confirmed by FPGA verifications. Therefore, this scheme is considered applicable in the next-generation high speed embedded interconnections.

Resistive random access memory (RRAM) is extensively concerned because of its excellent characteristics, namely, simple cell structure, high speed, low power and high density. The basic structure and operation principle of RRAM are presented. The promising RRAM technologies, such as 3D integration and multi-level storage, are discussed.

A novel encoding scheme with high speed and low power is proposed for folding and interpolating ADC. In the encoder,XOR-OR encoding algorithmand a novel serial-parallel Domino circuit are adopted. A novel method for wide-range error correction and bit synchronization is presented. Simulation results show that the proposed encoder has about 56% decrease on power delay product compared to conventional ROMencoder and this encoder is more applicable for the folding and interpolating ADC with higher resolution.

The authors propose an improved phased locked loop(PLL) architecture with dual control paths. The two control paths have different voltage controlled oscillat or (VCO) gain. The coarse tuning path has a large VCO gain, and is used to cover operating frequency range. Having a small VCO gain, the fine tuning path determines the loop bandwidth and optimizes the jitter performance. This circuit is fabricated in a 0. 18 μm CMOS logic process. The presented PLL has an output range from 600MHz to 1.6 GHz, and exhibits good jitter characteristic.

A novel ESD clamp protection circuit named gate, controlled SCR cascade diode string (gcSCR, CDS) is proposed. Compared with the traditional CDS device, this novel structure has a high ESD performance due to its low leakage current and low turn, on resistance by inserting a SCR transistor. A gate, controlled PMOS transistor is also used to immunize its latch, up effects. This new structure is performed in 0.35?μm CMOS process. The measured results show that it has a low leakage current about 12nA and a high ESD robustness above 8kV.